1. Field of the Invention
The present invention relates generally to an enhanced bitline equalization for hierarchical bitline architecture, and more particularly pertains to an enhanced bitline equalization for a hierarchical bitline architecture for high speed, high density and low power DRAM memories. The enhanced bitline equalization is designed to eliminate drifting of the bitline potential from the equilibrium voltage Vbleq caused by bitline unbalanced capacitances.
2. Discussion of the Prior Art
In a modern high density and low power memory design, using a hierarchical bitline architecture can increase the density of the memory array. A hierarchical bitline architecture allows more bitline pairs to share a common sense amplifier. Non-active bitlines are left floating except during a precharge and equalization period. During this period, the precharge devices must have the capability and be large enough to precharge all of the bitline pairs at once. However, large precharge devices can consume a substantial amount of power and require very large device sizes in order to perform this process within a reasonable period of time.
In the design of a conventional memory array, the precharge device is normally fabricated inside the sense amplifier, and is isolated by switch devices from all of the bitlines that are connected to it. The precharge devices are inherently not strong enough when the array size is large, and the Vbleq (bitline equalization) voltage is weakened and lower when it reaches the far end edge of the memory array. In this case, the floating bitlines are difficult to bring to the equalization voltage level, and also the active bitlines are difficult to equalize during the precharge period.
During the equalization period, an equalization voltage EQL is turned on first, so that Vbleq is supplied to the sense amplifier circuit. This process effectively brings the bitlines to the equalization level. Shortly thereafter, a dateline equalization voltage LDQEQ is turned on to equalize the GLDQ wirings. The reason for doing this is that the Vbleq supply is not strong enough to simultaneously bring all of the bitlines and the global DQ data buses to the equalization level.
In a conventional dynamic memory design, each sense amplifier is shared by many pairs of bitlines and the sense amplifier becomes weaker during the PC/EQ (precharge and equalization) period if the PC/EQ device components are also shared. Simulation test results indicate that the bitline equalization level drifts from cycle to cycle and finally saturates at an equilibrium value.
The cause of this drift is primarily attributed to the unbalanced bitline capacitance between the bitline pairs. To be more specific, the pFET device size in the latch circuit of the sense amplifier is more than twice the size of the NFET device in the latch circuit due to an inherently weaker driveability of the pFET device. Therefore, the capacitance load of the PCS node, which is connected to many sense amplifiers in the same block, is larger than the capacitance load of the NCS node, which is also connected to many sense amplifiers in the same block, due to the difference in device sizes. This effect in some bitline data patterns is further enhanced by a bitline loading mismatch and is thus reflected in the final voltage equalization level. This voltage level can be significantly different from the Vbleq (supplied equilibrium voltage), which is the equilibrium voltage of the bitlines before the onset of sensing.
Because the capacitive loading in the circuit is strongly voltage dependent, it is very difficult to avoid this drifting unless a stronger PC/EQ (precharge and equalization) component is used for each bitline pair, which is undesirable.
Accordingly, it is a primary object of the present invention to provide an enhanced bitline equalization for a hierarchical bitline architecture.
The present invention provides a new bitline sensing and balancing circuit for high speed, high density and low power DRAM memories which uses a bitline balancing technique designed to eliminate drifting of the bitline potential from the equilibrium voltage Vbleq caused by bitline unbalanced capacitances.
The drifting of the bitline potential from the equilibrium voltage Vbleq is reduced by adding an extra compensating capacitance element, such as a compensating capacitance element formed by conductor electrodes between the dielectric or in the FET structure, to equalize the capacitance loading between the NCS and PCS nodes of the sense amplifiers to eliminate drifting of the bitline balancing voltage. This results in a sense amplifier circuit with less devices, a high sensing speed and a lower power consumption.
Sensing signal noise can also be reduced by setting the timing of the EQ signal earlier than the MUX signal, and by the proper sizing of equalization devices.